It includes:
Student Learning Record (A3 version in word)- Student Learning Record (PDF version)
- Student Learning Record (PowerPoint version)
- Student Learning Record (Exemplars)
- Set of student activities and workshops with answers
- Answers to the exam questions from the back of the SLR
- Teacher Marking Checklist
- Year 13 Recap Lesson
H046
- 1.1.1 a-d Structure and function of the processor
H446
- 1.1.1 a-e Structure and function of the processor
Specific knowledge required for AS and A Level:
- Candidates need to have an understanding of the purpose and function of the core components of a processor.
- Candidates need to understand the role and components of the ALU.
- Candidates need to understand the purpose and function or registers within the processor, including the PC, accumulator, MAR, MDR and CIR.
- Candidates need to understand the purpose, function and role of the data, address and control buses in the processor.
- Candidates need to understand how assembly language makes use of registers, and how data and addressed are transferred between registers.
- Candidates need to understand the purpose and stages within the FDE cycle.
- Candidates need to understand how and when the registers are used within this cycle, and how and where data and addresses are transmitted to/from in each part of this cycle.
- Candidates need to understand how the performance of the CPU can be affected by many factors.
- Candidates need to understand how and why the performance is affected by the clock speed, the number of cores and the size and speed of the cache.
- Candidates need to have an understanding of the Von Neumann and Harvard architectures. They should be aware of the different approaches the architectures take to storing instructions and data in memory and the benefits of each approach.
- Candidates will not be asked about specific aspects of “contemporary processor architecture” unless explicitly named in the specification. They may, however, be asked to show an awareness of how contemporary processors differ from a pure Von Neumann architecture in more open questions.
